Staff Engineer, Digital Design Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and.

Staff Digital IC Design Engineer

The Data Center and Energy team at Analog Devices is seeking a STAFF DIGITAL IC DESIGN ENGINEER. The successful candidate will join a talented and motivated multi-disciplinary team, working with a global team of innovators to develop new industry-leading IC products for the high-growth data center and energy markets.

Responsibilities

Collaborate with applications engineers, analog leads, test and measurement leads, and customers to define and develop optimal system-level solutionsLead the digital development of mixed-signal IC products, working with a team of digital designers to define specifications, develop architectures and execute designs, including pre-silicon verification and post-silicon validationDevelop optimized solutions with consideration of performance, area, power, risk, resources, and scheduleEstablish and continuously improve development flows and methodologies for the teamSupport and review the work of physical design engineersParticipate in customer engagements, in support of technical feasibility and proposalsProvide mentorship and technical leadership, enabling a culture of continuous learning and improvement

Minimum Qualifications & Experience

Bachelors/Master's degree in electronics engineering or equivalent with 7+ years of experienceDigital design experience with multiple products introduced to the marketExperience in leading complex IC and IP developmentsBroad experience of digital design using Verilog / SystemVerilog RTL including clock domain crossings, timing constraints and synthesis.Good understanding of the full digital flow from RTL to GDS, including supporting place and route, LEC, STA and power analysis tasksKnowledge of Design For Test including scan insertion, ATPG and fault gradingUse of linting toolsVerification, including gate level simulationStrong technical and analytical background with good problem-solving skillsStrong team worker within multi-discipline, multi-cultural and multi-site environmentsGood understanding of mixed-signal design flow and top-down development methodologyExcellent written and verbal communication

Preferred Qualifications & Experience

Proficient with Cadence tool suiteScripting languages (Shell, TCL, PERL, Python)Analog behavioral models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)Mixed-signal verification methodology and tools (AMS / APS / Flex)IC top-level digital UVM verification (Universal Verification Methodology)Constrained-random verification, functional coverage and assertions

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Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days