Apple

  • St Albans, UK
Jan 28, 2023
Apple Swindon, UK
Key QualificationsExperience in P&R and flow developmentUnderstand various aspects of partition level PNR including floorplanning, power planning, placement, timing/power optimization, CTS, routing, UPFUnderstanding and exposure to extraction and timing analysis flowsUnderstand hierarchical P&R issues is a key (top-level floor planning, pin-assignment, clock-distribution, UPF, power-distribution, multi-voltage design, pad ring construction, placement, optimization, and routing)Strong scripting knowledge preferredProven track record of managing, and regressing P&R flowsYou should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologiesWe are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirementInnovus or ICC knowledge is a plusEnglish fluency is requiredDescriptionProvide innovative solutions to support and improve the...
Jan 28, 2023
Apple Cambridge, UK
Key QualificationsExperience in P&R and flow developmentUnderstand various aspects of partition level PNR including floorplanning, power planning, placement, timing/power optimization, CTS, routing, UPFUnderstanding and exposure to extraction and timing analysis flowsUnderstand hierarchical P&R issues is a key (top-level floor planning, pin-assignment, clock-distribution, UPF, power-distribution, multi-voltage design, pad ring construction, placement, optimization, and routing)Strong scripting knowledge preferredProven track record of managing, and regressing P&R flowsYou should be familiar with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologiesWe are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirementInnovus or ICC knowledge is a plusEnglish fluency is requiredDescriptionProvide innovative solutions to support and improve the...
Jan 28, 2023
Apple Cambridge, UK
Key QualificationsPrevious complex IP design experience is required.Experience working on GPUs is desirable but not required.Understanding of implementing modern design techniques.Hands on experience with energy-efficient and low-power logic design.Strong background in computer architecture including one or more of: high-speed CMOS processor and controller blocks, cache controllers, bus-interface subsystems, integer and floating-point numeric units, digital filters, graphics processors, crossbar fabrics and other high-speed data-path control units.Well-versed in logic optimisation, synthesis, timing analysis.Fluency with RTL Verilog/VHDL syntax & hardware modelling.Familiarity with logic simulation and debug environments as well as formal verification.Ability to work well in a team and be productive under tight schedules.Excellent communications skills, self-motivated and well-organised.DescriptionYou will work closely with other designers to refine GPU micro-architectural...
Jan 28, 2023
Apple St Albans, UK
Key Qualifications5+ years design experienceExperience in logic designUnderstanding of physical design and design for test (DFT)Proficiency in System Verilog, scripting languages (Perl/Ruby/Python/Tcl), programming languages (C, C++), and revision control systemsExposure to logic synthesisUnderstanding of computer architectureAbility to work well in a team and be productive under aggressive schedulesDescriptionParticipate in RTL Top-level assembly and triage of GPU designsPlan, create and execute all RTL deliveries to physical design & SoC teamsTake part in complex codeline management, supporting multiple products & chipsSupport integrating IP & design libraries Drive improvements and automation to frontend design flow — synthesis, CDC/RDC, LINT, etcWork closely with other teams to support design integrationEducation & ExperienceBSc/MSc/BEng/MEng/PhD in related field
Jan 28, 2023
Apple Irvine, UK
Key QualificationsPrefers extensive experience in Physical Design experience on high PHY and/or SOC designsDeep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraintsDeep understanding of all aspects of Timing flow, Physical construction, Integration and Physical VerificationConfirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixesShown experience in industry standard Timing, Physical Design and Synthesis toolsDeep Understanding of scripting languages such as Perl/TclDescriptionAs a Timing Design engineer you will be involved with all phases of physical design of dedication PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on...
Jan 28, 2023
Apple Irvine, UK
Key QualificationsBS and 10+ years of relevant industry experience.RF/analog and mixed-signal design experience in cutting-edge RF CMOS design.Direct experience in designing and bringing into mass production ZIF RF transceivers in deep sub-micron RFCMOS technology.Deep understanding of analog, mixed-signal and RF circuit design. This includes design of on-chip LNAs and PAs, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers, data converters and calibration methods associated with such high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for mass production environment.Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments.Deep understanding of CMOS device physics, RF device modeling, device noise parameters and inductor modeling.Familiarity with various RF transceiver architectures and their trade-offs, system...