Samsung
Goldstone, Market Drayton TF9 2NA, UK
Description /background:· Designing and developing CXL and DRAM controller (DDR4/5) based intellectual property. - Design and Engage with other architects within the IP level to drive the Micro-Architectural definition.· Deliver quality micro-architectural level documentation.· Produce quality RTL on schedule by meeting PPA goals.· Be responsible for the logic design/ RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. · Collaborate with the verification team to ensure implementation meets architectural intent. · Hands-on in running quality checks such as Lint, CDC and Constraint development.· Substantial background in debugging designs in the simulation environments. · Deep understanding of fundamental concepts of digital design Preferred Skill: · Strong Verilog/System Verilog RTL coding skills. · Experience with DRAM Memory Conytroller design.· Knowledge of DRAM standard (DDR4/5) memory.· Interface/Protocol experience required - AHB/AXI,...
