Apple
Irvine, UK
Key QualificationsPrefers extensive experience in Physical Design experience on high PHY and/or SOC designsDeep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraintsDeep understanding of all aspects of Timing flow, Physical construction, Integration and Physical VerificationConfirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixesShown experience in industry standard Timing, Physical Design and Synthesis toolsDeep Understanding of scripting languages such as Perl/TclDescriptionAs a Timing Design engineer you will be involved with all phases of physical design of dedication PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on...