5 jobs found in north ayrshire council

Business Line Description : NXP’s ultra-wideband (UWB) technology enables secure ranging and precision sensing, creating a new dimension of spatial context for wireless devices. UWB technology processes contextual information to ease decision making and precise device management. The fine ranging and positioning capabilities of the UWB products bring precise location and convenience to a variety of use cases, including secure access control, indoor positioning, device-to-device communication and item tracking. In NXP, we work on the entire secured UWB platform that includes the hardware implementation and the software development.Job Summary:Responsible for design, simulation and implementation of radio blocks for wireless connectivity applications. Work with system team on architecture design and block specifications. Evaluate the design in the lab and support for the mass productionKey Challenges:You will be part of a growing team, working on leading SoC chips for various Mobile...

Key QualificationsPreferred validated experience in IP design integration and implementation with multiple clock domains and multiple power domains.Deep knowledge and experience in various tools such as RTL simulation, lint, logic equivalence, version control, synthesis, static timing analysis, CDC, RDC in order to generate gate level netlist and perform various checks.Working experience with the physical design teamsDeep knowledge of VLSI design methodology ranging from RTL to sign-off and familiarity with programming language such as Perl, Tcl, shell scriptsThe ideal candidate will be familiar with version control, CVS, Perforce, ClearCase.Excellent interpersonal skills and interaction experience with sub block owners, physical design teams and different engineering groupsDescriptionAs a senior IP Design/Implementation engineer you will have responsibilities spanning all aspects of IP. You will be responsible for generating gate level netlist and various collaterals for physical...

Key Qualifications10+ years of experience in analog/mixed-signal layout design of deep sub micron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFet technologiesHigh level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reportsExperience with CADENCE or MENTOR GRAPHICS layout toolsProgramming knowledge in SKILL, Perl, and/or Python is a bonusDescriptionSenior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCsEducation & ExperienceB.S. EE & CS or equivalentApple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who...

Key QualificationsTypically requires 15+ years of RF/analog and mixed-signal design experience, with 7+ years management experience in cutting-edge RF CMOS design.Direct experience in designing and bringing into mass production ZIF RF transceivers in deep sub-micron RFCMOS technology.Deep understanding of analog, mixed-signal and RF circuit design. This includes design of on-chip LNAs and PAs, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers, data converters and calibration methods associated with such high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for mass production environment.Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments.Deep understanding of CMOS device physics, RF device modeling, device noise parameters and inductor modeling.Familiarity with various RF transceiver architectures and their trade-offs,...

Key QualificationsPreferred at least 5+ years of Physical Design experience on high PHY and/or SOC designsDeep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraintsDeep understanding of all aspects of Timing flow, Physical construction, Integration and Physical VerificationConfirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixesExperienced user of industry standard Timing, Physical Design and Synthesis toolsDeep Understanding of scripting languages such as Perl/TclDescriptionAs a Timing Design engineer you will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on...