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London Borough of Lambeth, London, UK
FPGA Design Engineer (Senior / Principal) – 5G (O-RAN PHY) Permanent – £70,000 to £100,000 basic salary, plus 10% bonus, share options, 25 days holiday (plus stats), pension, life insurance, healthcare etc.. This role can be performed fully remotely. FPGA Design Engineer with expertise in digital design using Verilog, Vivado and, QuestaSim required by innovative, international 5G solutions provider. The Senior / Principal FPGA Engineer will play an important role as an individual contributor within an international team tasked with the development of a range of products with broad commercial applications within the telecommunications sector. Key skills: * 8+ years of Digital IC Design (FPGA / ASIC) expertise from architecture through to design and verification * Strong skills in front end RTL design using Verilog / SystemVerilog as well as simulation tools (eg. QuestaSim or ModelSim) * Strong skills in Xilinx FPGA designs, with expertise in Vivado design suite * Strong...