2 jobs found in irvine

Key QualificationsPrefers extensive experience in Physical Design experience on high PHY and/or SOC designsDeep knowledge of industry standards and practices in Timing closures, Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route Experience in developing and implementing STA constraintsDeep understanding of all aspects of Timing flow, Physical construction, Integration and Physical VerificationConfirmed knowledge of Basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixesShown experience in industry standard Timing, Physical Design and Synthesis toolsDeep Understanding of scripting languages such as Perl/TclDescriptionAs a Timing Design engineer you will be involved with all phases of physical design of dedication PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block level static timing constraints. Close timing on...

Key QualificationsBS and 10+ years of relevant industry experience.RF/analog and mixed-signal design experience in cutting-edge RF CMOS design.Direct experience in designing and bringing into mass production ZIF RF transceivers in deep sub-micron RFCMOS technology.Deep understanding of analog, mixed-signal and RF circuit design. This includes design of on-chip LNAs and PAs, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers, data converters and calibration methods associated with such high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for mass production environment.Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments.Deep understanding of CMOS device physics, RF device modeling, device noise parameters and inductor modeling.Familiarity with various RF transceiver architectures and their trade-offs, system...